(General Background Art)
In recent years, there have been enthusiastic studies on active matrix display apparatuses in which every pixel electrode of the liquid crystal panel is provided with a thin film transistor (hereafter referred to as TFT) because of their higher image quality than simple matrix display apparatuses. Above all, so-called built-in driving circuit-type liquid crystal display apparatuses, in which TFTs as pixel switching elements and driving circuits are mounted on the same glass substrate with the use of polysilicon, have been suggested and studied because the mobility of electrons in the polysilicon TFT is one or two digit higher than that of the amorphous silicon TFT.
However, the polysilicon TFT used to build the driving circuit in has a larger OFF current than the amorphous TFT or the MOSFET, and this problem will hinder the realization of the built-in driving circuit-type liquid crystal display apparatus with polysilicon TFTs.
In order to solve this problem in electronic properties of the polysilicon TFT, it has been suggested and studied to realize a TFT structure where the OFF current is reduced and the ON current is maintained by forming a sub-gate structure and provide an low concentration impurity-doped region (LDD: Lightly Doped Drain) adjacent to at least one of the source and drain regions of a TFT (SID96 DIGEST pp25: Samsung electron, Euro Display '96 pp555, ASIA Display'95 pp355: Philips).
The structure of such a thin film transistor is shown in FIG. 1.
In the figure, numeral 1 denotes a glass substrate having a buffer layer for preventing the internal substances from migration on the upper surface (in the drawing) thereof. Numeral 2 denotes a polysilicon semiconductor layer. Numeral 3 denotes a gate insulator film. Numeral 4 denotes a gate electrode. Numeral 40 denotes a sub gate electrode, and numerals 45 and 46 on the left and right portions thereof denote sub gate electrodes of which ends sticking out in the channel direction. Numerals 245 and 246 denote low concentration impurity doped regions (hereinafter often referred to as LDD regions) of the polysilicon semiconductor layer 2. Numeral 25 denotes a source region (n+ layer) of the layer. Numeral 26 denotes a drain region (n+ layer) of the layer. Numeral 24 denotes a channel region of the layer. Numeral 5 denotes a source electrode. Numeral 6 denotes a drain electrode. Numeral 7 denotes an interlayer insulator film.
In actual, a number of such TFTs shown in the figure are formed on a glass substrate of 30 cm×40 cm or so in row and column manner in accordance with the arrangement of pixel areas and driving circuit units in their vicinities, and necessary with wirings. However, they are not illustrated because of being obvious.
On the gate electrode 4 of this TFT, the sub gate electrode 40 is provided so as to cover the electrode, and the low concentration impurity-doped regions (LDD region: n− layers) 245 and 246 are formed directly below the portions 45 and 46 of sub gate electrode, both sticking out from the gate electrode 4.
These low concentration impurity-doped regions are generally formed as follows. After forming the gate electrode 4, injection of low-concentration impurities are made into the polysilicon semiconductor layer 2 beneath the gate insulator film via the gate insulator film by using the gate electrode 4 as a mask. Thus, the region directly below the gate electrode is prevented from injection of impurities thereby a channel region is formed on this region of the polysilicon semiconductor layer. Then the remaining regions, which are not covered by the gate electrode 4, are lightly doped with the impurities.
Next, a metal film which is to be processed into the sub gate electrode 40 is formed on the gate electrode 4 and unnecessary portions of the metal film are removed by photolithography and etching to form the sub gate electrode 40 made of the metal film which covers only the top and side surfaces of the gate electrode. As a result, the sub gate electrode 40 has end portions 45, 46 sticking out in a predetermined amount in the channel direction (in the direction of the source electrode and the drain electrode).
Finally, impurities of far higher concentration than those injected earlier are injected.
Hence, the regions of the semiconductor layer that are not covered with the sub gate electrode are heavily doped with impurities thereby the source region 25 and the drain region 26 are formed, whereas the portions covered with the sub gate electrode are not doped with impurities thereby the low concentration impurity-doped regions 245 and 246 are formed directly below the portions sticking out from the gate electrode. The size of the low concentration impurity-doped regions is set at 100-10% of the channel width of the TFT.
As described hereinbefore, in the polysilicon TFT, in order to overcome the drawback of the electric property that the OFF current is large, it is essential to provide a minuscule low concentration impurity-doped region (LDD: Lightly Doped Drain) adjacent to at least one of the source region or the drain region of the TFT.
(Background Art in Terms of the Problems the Invention is Going to Solve)
However, the formation of these low concentration impurity-doped regions accompanies with the following problems.
1) Achieving high fineness in a liquid crystal display apparatus requires increasing the display density by downsizing pixel transistors. An exposing device most commonly used for the fabrication of a liquid crystal display apparatus is a proximity exposure unit. Although it is necessary in the fabrication of a minuscule pixel transistor to form a low concentration impurity-doped region as small as 10-25% of the channel width of the pixel transistor with precise dimensions and good reproducibility, this is therefore extremely difficult.
2) The sub gate electrode and the low concentration impurity-doped regions are positioned by a mask positioning; however, it is difficult to position them with high precision. For this, a small amount of deviation in the mask positioning may cause the dimensions of the low concentration impurity-doped regions to vary more than an ignorable degree in the actual use. Therefore, in order to secure the margin for the mask positioning in the fabrication process, the pixel TFT can become minuscule only in a limited range, and the pixel TFT must take up an extra area for the margin.
3) The pixel TFT takes up a larger area, which increases the parasitic capacitance between source region and drain region, thereby causing a delay in the operational waveform, leading to a decrease in the display properties of the liquid crystal display apparatus.
4) The formation of the sub gate electrode requires some processes, besides for the formation of the gate electrode, such as forming a metal film, photolithography and etching, and further requires a photomask for the photolithography. The TFT fabrication is thus complicated, possibly causing an increase in the production time and cost, and a decrease in the yield.
Although it is not limited to the LDD thin film transistor, there has been the demand of minimizing undesirable influence by the hydrogen implanted at high energy to dilute impurities at the time of injection to the crystalline structure of the semiconductor.
There is the other demand for low electric resistance in each component so as to obtain display properties of high quality such as uniform brightness across a large display surface, and at the same time, for simple fabrication with a low cost.
In a display apparatus, the properties required for transistors differ, for example, between the pixel unit and the peripheral circuit unit. In some type of devices, there is the demand for an offset transistor having no impurity-injected regions both ends of the channel region provided below the gate electrode in the channel direction.
Therefore, in order to reduce the OFF current and to maintain the ON current of the polysilicon thin film transistor, it has been hoped to realize the art of fabricating a thin film transistor with small parasitic capacitance in an extremely simple manner by forming minuscule LDD regions with high fineness adjacent to the source region and the drain region of the TFT either in a self-aligned manner or inevitably adjacent to the gate electrode without a special mask positioning process.
The development of the same technique has been hoped for the offset transistor.
It is also hoped for other types of transistors having various properties, besides the LDD transistor and the offset transistor.